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My name is Greg Gibeling, I grew up in Davis, California.
I worked as an embedded systems programmer at JK microsystems and
a window kernel developer at CACE Technologies. I have received
a bachelors and masters in EECS at
U.C. Berkeley where I spent two years as the Head TA for
EECS150, the digital systems course, and one
semester as Head TA for CS61C the lower division
machine structures and C programming course.
I am currently a 5th year PhD student in EECS at
U.C. Berkeley. In the past I worked on the RAMP
project developing design tools, models and infrastructure for FPGAs-based processor simulation.
I am currently working on GateLib: a library for hardware and software research, and RePar:
new abstractions and tools for productivity and performance in reconfigurable parallel computing.
The goal of the RePar project is to explore tools and algorithms for synthesizing high quality hybrid
systems from high level application descriptions. GateLib provides a necessary foundation for
generating and testing this work, and is shared with a number of other projects.
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