Greg Gibeling

There are two projects that will become more publicly visible over the next few months, through this website and others.

RePar

Through the use of a novel representation, called Dataflow Stencil, for computing applications we can combine ideas from high level synthesis, parallel computing and high productivity programming. This in turn enables the creation of a Solution Compiler, capable of synthesizing simple high level descriptions into high performance, parallel implementations on hardware platforms ranging from FPGAs to CPUs, and combinations in between.

This is my PhD research, and will include the P language, the Solution Compiler, the Dataflow Stencil libraries, and much more. Of course there will also be a significant amount of documentation.

GateForge

I've had the domain name for quite some time, and yet never managed to put anything on it until now. GateForge will be the development side for projects like RePar mentioned above, and GateLib, an extensive library of software and hardware components. In addition to providing downloads and source repository access, over time GateForge will allow these projects to transcend the U.C. Berkeley IT problems which have limited their accesability to non-researchers.

1. [ZIP] Greg Gibeling, RDLC, 5/20/2008, version 2.2008.5.20
2. [PDF1][PDF2] Greg Gibeling, RDLC2: The RAMP Model, Compiler & Description Language, 5/20/2008, UC Berkeley
3. [ZIP] Greg Gibeling, Templates, 3/2/2008
4. [PDF] Andrew Putnam, Greg Gibeling, RAMP Tools & Infrastructure, 1/17/2008, RAMP Winter Retreat 2008
5. [PDF] Greg Gibeling, Third Time’s The Charm: Designing & Building RDLC3, 1/16/2008, RAMP Winter Retreat 2008

My name is Greg Gibeling, I grew up in Davis, California and have received a bachelors and masters in EECS at U.C. Berkeley. In the past I have worked as an embedded systems programmer at JK microsystems and a window kernel developer at CACE Technologies. I also spent two years as the Head TA for EECS150, the digital systems course at U.C. Berkeley and one semester as Head TA for CS61C the lower division machine structures and C programming course.

I am currently a 4th year PhD student in EECS at U.C. Berkeley working on the RAMP project. Specifically I am working on RAMP Gold, a highly parameterizable, scalable and cycle accurate computer architecture simulator implemented in FPGAs. The goal is to scale to thousands of simulated processor cores with significantly less than a 1000x slowdown compared to real-time.

On the side I am developing RCF and RDLC3, the third major version of the RAMP Description Language compiler which is designed to compile the timing accurate hardware level distributed systems, including a full abstration of communication, support for powerful debugging tools and support for co-simulation between various hardware and software platforms.