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My name is Greg Gibeling, I grew up in Davis, California and have received
a bachelors and masters in EECS at U.C. Berkeley.
In the past I have worked as an embedded systems programmer at JK microsystems and
a window kernel developer at CACE Technologies. I also spent two years
as the Head TA for EECS150, the digital systems course
at U.C. Berkeley and one semester as Head TA for CS61C the
lower division machine structures and C programming course.
I am currently a 4th year PhD student in EECS at
U.C. Berkeley working on the RAMP
project. Specifically I am working on RAMP Gold, a highly parameterizable, scalable and cycle accurate computer
architecture simulator implemented in FPGAs. The goal is to scale to thousands of simulated processor cores with
significantly less than a 1000x slowdown compared to real-time.
On the side I am developing RCF and RDLC3, the third major version
of the RAMP Description Language compiler which is designed to compile the timing accurate
hardware level distributed systems, including a full abstration of communication, support for powerful debugging tools
and support for co-simulation between various hardware and software platforms.
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